The present technology relates to a memory device and to techniques for operating a memory device.
Recently, ultra high density storage devices have been proposed using a three-dimensional (3D) stacked memory structure. One example of a 3D memory structure is the Bit Cost Scalable (BiCS) architecture which comprises a stack of alternating conductive and dielectric layers. A memory hole is formed in the stack and a NAND string is then formed by filling the memory hole with materials including a charge-trapping layer. A straight NAND string extends in one memory hole, while a pipe- or U-shaped NAND string (P-BiCS) includes a pair of vertical columns of memory cells which extend in two memory holes and which are joined by a bottom back gate. Control gates of the memory cells and of select gate transistors are provided by the conductive layers.
Each memory cell has a charge storage region such as a dielectric charge trapping region or a conductive floating gate. A memory cell may be programmed by applying a programming voltage to its control gate to add or remove charge from its charge storage region, thereby altering the threshold voltage of the memory cell.
However, various challenges exist in programming such memory devices.